Modern flyback converters are operated in quasi resonant fashion during operation at nominal power, i.e. their specified continuous power, in order to achieve a high efficiency. The quasi resonant mode is, in principle, the operating point between intermittent and continuous operation at a variable frequency and a variable duty ratio. FIG. 12 shows the basic circuit diagram of such a converter 1. Low-loss switching at the power converter switch is achieved by the power converter switch, here a transistor Q1, being switched on if the voltage Vds across the power converter switch falls to almost zero volts after complete outputting of energy by the secondary circuit L2. If regulation to the primary current Ip of a converter transformer T1 is effected (current mode), Q1 is switched off if the primary current Ip has reached the setpoint value stipulated by a regulating system 2.
The profiles of currents and voltages are illustrated in FIG. 13. After the transistor Q1 has been switched on, the primary current Ip in the primary winding L1 of the converter transformer T1 rises until the setpoint value is reached. No secondary current Is flows in the secondary winding L2 at this point in time. After the transistor Q1 has been switched off, the primary current is zero, and a secondary current Is flows. If the secondary current has fallen to the value zero again, the transistor Q1 is switched on again. The voltage Vds has fallen to almost zero volts at the switching instant.
In this way, the regulating system 2 generates a pulse-width-modulated signal for controlling the transistor Q1. The pulse-width-modulated (PWM) signal is characterized by the frequency fpwm (fpwm=1/Tpwm) and the duty ratio D. Changing load conditions at the output (RL) and changing input voltage conditions lead to a variation of frequency fpwm and duty ratio D.
In conventional analog technology there are a multiplicity of pulse width modulation controllers which take account of this operating mode. Digital pulse width modulation units in microcontrollers are likewise able to ensure this operating mode.
When using cost-effective 8 bit microcontrollers and converter frequencies of between 250 kHz and 500 kHz, however, there is only a very limited choice of microcontrollers which comprise a pulse width modulation unit enabling said operating mode.
One example of such a microcontroller is the PIC16F785 from the company MICROCHIP (see PIC16F785/HV785Data Sheet, MICROCHIP DS41249D). This is an 8 bit CMOS microcontroller having an integrated pulse width modulation unit. Various operating modes are supported by the pulse width modulation unit, e.g. single-, dual-phase or single complementary PWM.
FIG. 14 shows the basic construction of the pulse width modulation unit 20 of such a microcontroller in the complementary output operating mode. A clock signal pwm_clk for a phase counter 202 is usually generated directly from the processor clock Fosc; a prescaler 204 can be configured. The maximum period duration of the switch-on phase is configured by Bit 0 to Bit 4 (PER <4:0>), in a pulse width modulation clock control register PWMCLK (not shown). The phase counter 202 increments its register by one upon each clock pwm_clk. If the value of the phase counter 202 (PWM_COUNT) reaches the value which is defined in PER and which represents the maximum period duration, the phase counter is reset to zero. A prerequisite for this is that the pulse width modulation unit 20 operates in the single master mode, that is to say that the pulse width modulation unit 20 operates by itself and other pulse width modulation units are not involved.
The mode of action of the duty ratio is defined in the pulse width modulation configuration register PWMCON1 (not shown). If an internal comparator 206 of the microcontroller is used for the comparison of the primary current with the setpoint-value regulator stipulation (current mode) and if the intention is to stipulate a maximum duty ratio at the minimum frequency of the pulse width modulation signal, it is necessary to end the switch-on time e.g. by precisely the comparator 206 of the microcontroller. A register PWMPH2 in combination with a gate 208 is additionally used in order to end the switch-on time of the present pulse width modulation period independently of the comparator 206. If the output of the gate 210 is not equal to zero and the output of the gate 208 is equal to zero, the switching output SQ1 is activated if the phase counter PWM_COUNT has reached the value zero, and the next clock of the pulse width modulation clock is present. The switching output SQ1 becomes inactive if comparator 206 is set as active or the phase counter PWM_COUNT has reached the value of the register PWMPH2 (PWM_COUNT=PWMPH2). Since the internal comparator outputs affect the resetting of the switch-on time of the pulse width modulation signal asynchronously, i.e. independently of the pulse width modulation clock, in this component there are no digital resolution errors with regard to the duty ratio. In this configuration, it is readily possible to drive the transistor Q1 of a flyback converter 1, although only in a continuous mode. Continuous mode hereinafter denotes a pulse-width-modulated operation mode with a variable duty ratio and fixed pulse width modulation frequency without low-loss switching of the transistor Q1. In addition, the pulse width modulation unit 20 has an input 212 enabling the pulse width modulation outputs to be inactivated when exceptional situations occur (e.g. overvoltage, overcurrent, etc). When such an event occurs, the phase counter 202 is reset to zero and the pulse width modulation outputs SQ1 and SQ1 remain inactive. If the exceptional event disappears, the pulse width modulation unit 20 starts automatically and the pulse width modulation outputs are enabled again with a delay by a clock of the pulse width modulation clock (PWM_CLK) if the port PRSEN in the configuration register PWMCON0 is set.
With such a microcontroller it is possible, in principle, to react to the occurrence of a Vds event (reduction of the voltage Vds at the power converter switch Q1 towards zero volts) if transistor Q1 is switched off. This is effected via the abovementioned input 212 for inactivating the outputs when exceptional events occur. On closer consideration, however, a temporal resolution problem arises: in order to notify the microcontroller that a Vds event has taken place, an active low signal having the pulse length t_tr is provided in said input.
The pulse length t_tr of the signal must have at least the length of the period duration of a pulse width modulation clock in order that the event is reliably registered in the pulse width modulation unit. Since the pulse is not generated synchronously with the pulse width modulation clock, the pulse length must even be longer than a period of the pulse width modulation clock, greater than 125 ns in the example of the microchip microcontroller with a clock frequency of 8 MHz and a prescaler ratio of 1:1 of the prescaler 204. Taking into account the microcontroller's RC oscillator, which does not have quartz crystal accuracy, a pulse length t_tr of 175 ns is defined, that is to say that a minimum of 1 pulse width modulation clock cycle or a maximum of 2 pulse width modulation clock cycles elapse for registering the Vds event in the pulse width modulation unit. After the registering, the period counter is reset to zero and the outputs of the pulse width modulation unit are deactivated. After the Vds event has disappeared, a further pulse width modulation clock cycle is required in order to reactivate the output PH1, that is to say that a minimum of 175 ns or a maximum of 300 ns elapse from the occurrence of the Vds event until the transistor Q1 is switched on. These two cases are illustrated in FIG. 15. At a converter frequency of 500 kHz, a period duration is 2 μs. In an exemplary embodiment that will be discussed in greater detail later, the time from a voltage zero crossing to the next voltage maximum is just 300 ns. Consequently, the temporal resolution for the quasi resonant mode is much too low, and the clock cycle times are too slow, to enable zero-voltage switching (ZVS) of the transistor Q1. Therefore, when using comparable microcontrollers having pulse width modulation units of similar performance, the problem arises that a flyback converter with the boundary conditions already mentioned cannot be used for quasi resonant operation with ZVS and a good efficiency associated therewith, because the pulse width modulation unit is not able to switch on the transistor Q1 at the required point in time.